Senior Digital Verification Engineer

VeroTech

Antwerpen, Belgium

Your mission

You will play a pivotal role in advancing digital design through meticulous verification processes. Your expertise will be crucial in the development, verification, and validation of IP and system-level test cases for cutting-edge SoC/ASIC components. Your responsibilities will include:

Leading and managing digital verification efforts, ensuring the integrity and functionality of digital components
Developing and executing comprehensive verification plans and testbenches, leveraging your expertise in SystemVerilog and UVM
Collaborating closely with the verification team to monitor progress, troubleshoot issues, and ensure timely completion of verification tasks
Engaging in issue reporting and tracking, contributing to the continuous improvement of verification methodologies and processes

Your experience

A Master's or PhD in Electronics or Electrical Engineering
A minimum of 7 years of experience in digital verification, with a strong background in SystemVerilog and UVM
Demonstrated experience in IP and system-level verification
Proficiency in English, with excellent communication skills to effectively collaborate within a team

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