Define verification strategy as per system requirements. Support testbench architecture, verification plan, and interact with design teams for feature extraction.
Perform analog/real-number behavioral modelling and validation.
Integrate analog models in UVM-based digital/analog mixed-signal testbench.
Perform execution of verification plans, including AMS top-level self-checking verification.
Support technical communication with customers and participate in design reviews; ensure schedule adherence and interactive problem solving.
Who we are looking for
Master’s or Bachelor’s degree in Electrical Engineering with emphasis in Analog Mixed-Signal Verification or a similar specialty, as well as at least 10 years of proven industry experience.
Expertise in block- and system-level verification with reusable components, testbench architecture and verification planning.
Experience with analog behavioral modelling with System Verilog RNM and Verilog-AMS.
Experience with analog checkers; knowledge of SVA is a plus.
Experience with relevant EDA tools and familiarity with scripting languages (e.g. Python, Tcl, SKILL).
Fluent in English. Excellent team player; calm professional demeanor and excellent listening skills, ability to organize and prioritize work.
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