Full Custom ASIC Analog Layout Engineer

Imec

Leuven, Belgium

Are you a highly motivated Layout engineer with a passion for Analog IC layouts? Is your ambition to work in a diverse environment amongst some of the top researchers and engineers in the world? Are you an excellent communicator who thrives on a multi-disciplinary team? If so, please keep reading.

We are seeking an experienced Analog Layout Engineer who would like to make a difference by contributing towards designing the Analog Layouts in various technology nodes.

Who we are

As Full Custom Analog Layout Engineer, you join the Design Services Custom Layout team. This team specializes in full-custom IC layout for advanced analog, mixed-signal, and RF circuits. We support customers and internal programs across the complete ASIC development lifecycle, from design implementation and layout optimization to verification and tape-out, ensuring high performance, manufacturability, and compliance with advanced process technologies.

What you will do

Design Analog Layouts like PLL, BG, LVDS, IVREF etc. for various projects for Space Application and various other Research projects at Imec;
Perform physical verifications like DRC, LVS, EM/IR and other applicable checks for the designed blocks;
Perform floor plan and top-level routing, keeping in mind the various power domains, and various challenges associated with mixed signal design;
Perform all CHIP level validations post Dummy fill and other sign-off checks necessary for the tape-out;
Provide all the deliverables on time to meet the Project deadlines;
Archiving of all the reports and checklists at the end of the Project;
Contribute various Layout guidelines, checklists and other documents for various Technology nodes.

Who you are

Master’s degree (or equivalent through experience) in Electronics or Electrical Engineering;
Good experience in designing various Analog Blocks and for Top Level integration of these blocks and signoff checks;
Knowledge to design layouts in FINFETs and other advanced SOI nodes;
Sound knowledge of EDA Tools;
Understanding of Layout Dependent Effects for deep submicron technology nodes;
Tape-out experience in advanced process technology nodes is preferable;
Knowledge about Radiation Hardening and its implementation in Layouts;
Knowledge about svn, cliosoft or any other versioning tool;
Fluent in English, you bring strong communication skills, enabling effective collaboration across multidisciplinary teams.