Senior Manager Physical Design Engineer

AMD - Advanced Micro Devices

Cambridge, United Kingdom

THE ROLE

Are you an accomplished Physical Design leader passionate about pushing the boundaries of microprocessor design? Do you thrive on optimizing for Power, Performance, and Area (PPA) while leading dynamic, cross-functional teams? AMD is seeking a Senior Manager, Physical Design to lead a critical team focused on next-generation CPU Core implementation and signoff.

The Person

We're looking for a seasoned leader with deep expertise in Microprocessor Physical Design and advanced design techniques. You possess an unyielding commitment to achieving optimal Power, Performance, and Area (PPA) targets. This role demands exceptional people leadership and teamwork skills, as you'll be instrumental in guiding cross-geographical teams to success. Your strong analytical and problem-solving abilities will be key in collaborating with and influencing both executive-level technical experts and management to drive flawless execution.

Key Responsibilities

Lead and manage a high-performing team of engineers dedicated to Microprocessor Physical Design implementation and signoff;
Apply your extensive knowledge and hands-on experience in Physical Design, Timing Closure, and Signoff to deliver high-quality, on-time results for large, challenging, and leading-edge CPU Core designs;
Mentor, coach, and foster the growth of the CPU Core Physical Design Team, emphasizing a positive influence on team morale and culture;
Provide technical leadership and oversight across all facets of Physical Design, including:
- Full Chip Floor planning;
- Clock Tree Synthesis (CTS);
- Placement and Optimization;
- Routing;
- Parasitic Extraction;
- Static Timing Analysis (STA);
- IR/EM analysis;
- Physical Verification;
- Final Signoff.
Collaborate closely with RTL teams to continuously enhance PPA metrics;
Drive flow development and automation scripting;
Utilize strong technical problem-solving and debugging skills to overcome complex design challenges.

Preferred Experience

Hands-on experience in SoC Physical Design implementation, signoff, and TapeOut;
Proven leadership experience managing Physical Design teams of 10+ members;
Exceptional analytical and problem-solving skills, coupled with meticulous attention to detail;
Strong communication skills (written, verbal, and presentation) and excellent time management;
Proficiency with industry-standard EDA tools for Physical Design and Signoff flows, such as:
- Synopsys FusionCompiler, PrimeTime, StarRC;
- Cadence Innovus;
- Mentor Graphics Calibre;
- Apache Redhawk.
Demonstrated experience leading technical teams through complex design cycles;
Background in high-speed microprocessor designs;
Familiarity with current sub-micron technologies;
Solid understanding of Physical Design tools and flows, or custom circuit design.