Principal Engineer, Design Verification Engineering

Principal Engineer, Design Verification Engineering

ADI - Analog Devices

Dublin, Ireland

The PWC organization is looking for a motivated and enthusiastic Principal Engineer, Design Verification Engineering. The candidate will work with experts in the power engineering team to verify industry-leading DC-DC converter controllers, and will interact with digital design, analog design, and silicon design evaluation teams.

Responsibilities include, but not limited to:

• Provide technical leadership for design verification of mixed-signal power converter controllers from architecture through silicon bring-up, driving verification strategy, scope, and execution.
• Own and maintain end-to-end verification plans, including test strategy, stimulus generation, checkers, scoreboards, and sign-off criteria aligned with product requirements.
• Develop and review SystemVerilog/UVM testbenches for digital and AMS verification, leveraging reusable verification components, constrained-random stimulus, and robust self-checking methodologies.
• Work closely with analog, digital, and system architects to translate system requirements into verifiable specifications and define closure metrics through reviews and traceability.
• Drive coverage methodology and closure (functional, code, assertion), define meaningful metrics, and ensure verification completeness for tape-out readiness.
• Champion best-practice verification sign-off including Gate level simulation (GLS), LINT, CDC/RDC, reset/X-prop strategies, assertions (SVA), and formal/semi-formal techniques where applicable.
• Build and maintain scalable regression infrastructure (automation, dashboards, triage) and enable continuous integration practices to improve quality and reduce turnaround time.
• Lead AMS verification using behavioural models (e.g., Verilog-AMS/real-number models) and mixed-signal co-simulation to validate control loops, interfaces, and system interactions.
• Partner with design evaluation and applications teams to support silicon bring-up, correlate simulation to lab results, root-cause issues, and feed learnings back into verification and design.
• Lead verification reviews and risk assessments, communicate status/quality metrics to stakeholders, and drive cross-team alignment on priorities, schedules, and deliverables.
• Mentor and develop other verification engineers, set coding/review standards, and drive continuous improvement of methodologies, tooling, and reusable verification IP.

Minimum Qualifications:

• BSEE/BSCS (or equivalent) + 12+ years of relevant experience in IC design verification; advanced degree a plus.
• Proven technical leadership delivering verification for multiple ICs from concept through tape-out, including ownership of verification plans and sign-off readiness.
• Strong hands-on expertise in SystemVerilog/UVM, constrained-random verification, self-checking testbenches, and debug/triage of complex failures.
• Demonstrated ability to mentor engineers and influence cross-functional stakeholders through clear technical communication and effective reviews.
• Experience with verification sign-off practices (coverage closure, assertions/SVA, LINT, CDC/RDC, formal/semi-formal) and driving quality metrics to closure
• Demonstrated experience in verification techniques for one or more of the following, Processor subsystems/DSP/Power controllers/Formal verification
• Willingness to travel globally up to ~10%.

Preferred Qualifications & Experience:

• Experience with industry-standard digital verification simulators and flows (e.g., Xcelium/VCS/Questa) and strong familiarity with waveform/debug tooling.
• Experience with verification quality and sign-off tools such as LINT, CDC/RDC, and/or formal verification; able to define and enforce sign-off criteria.
• Strong scripting and automation skills (Python, Tcl, shell, Make) to build/maintain regressions, dashboards, and CI pipelines.
• Behavioral modeling and AMS verification techniques (e.g., real-number models, Verilog-AMS) and mixed-signal co-simulation experience.
• Comfortable using AI tools to support and accelerate verification tasks
• Domain knowledge of integrated power management (e.g., buck/boost converters, control loops, fault protection) and ability to translate system behavior into robust verification scenarios.