Senior ASIC Physical Design Engineer

Senior ASIC Physical Design Engineer

ARQUIMEA

Madrid, Spain

Technical Requirements:

• Experience in automated synthesis and timing driven place and route of RTL blocks;
• Experience in automated clock tree synthesis, design optimization, and design cycle time reduction;
• Experience in floor planning, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff;
• Good knowledge of back-end tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation, e.g.: Genus, Innovus, Tempus, APRISA, Catapult, etc

Required skills, experience and candidate profile:

• Telecommunications engineering, electronic engineering or equivalent;
• Master in micro-electronics or applicable experience in the field;
• Experience with scripting in python, TCL, Bash, etc.;
• +5 years of experience in back-end ASIC design.