CAD Physical Design Methodology Engineer

Qualcomm

Cork, Ireland

About the Role:

Join Qualcomm’s Global CAD organization and help shape the RTL‑to‑GDSII reference flows that power our next‑generation SoCs.

In this highly visible role, you’ll build and deploy advanced Physical Design methodologies and automation that improve PPA (Power, Performance, Area), quality, and design turnaround time across leading‑edge technology nodes (sub‑3nm).

You’ll collaborate with PD, IP, DTCO, and EDA partners worldwide, operating at the intersection of technology enablement, flow innovation, and production execution with a strong culture of learning and cross‑site collaboration.

Key Responsibilities:

Lead technology enablement and develop scalable reference flows for advanced process nodes (sub‑4nm), addressing deep sub‑micron design challenges;
Collaborate closely with EDA vendors to deliver production‑ready toolchains and drive continuous improvements in PPA across multiple design blocks;
Partner with core and SoC design teams to define and implement solutions for advanced multi‑die architectures and next‑generation technology nodes;
Validate end‑to‑end physical design solutions across synthesis, place‑and‑route, timing sign‑off, and physical verification;
Work cross‑functionally with EDA vendors, physical design, and IP teams to diagnose and resolve issues related to technology enablement and PD execution.

What We’re Looking For:

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field (Master’s degree preferred);
Strong foundation in CMOS circuit design and core VLSI concepts;
Minimum of 3 years of hands on experience in Physical Design, including:
- Floorplanning expertise for advanced technology nodes (4nm and below);
- Proven Place & Route experience using Synopsys Fusion Compiler and/or Cadence Innovus;
- In depth knowledge of placement optimization, clock tree synthesis (skew balancing), congestion mitigation, and legalization;
- Experience with DRC debugging and sign off physical verification using Calibre;
- Solid understanding of technology LEFs, standard cell libraries, and advanced node DRC rule decks;
- Demonstrated ability to deliver PPA critical designs and make informed architectural and implementation trade offs;
- Timing closure experience using PrimeTime and/or Tempus, along with IR analysis and GDS generation.
Strong scripting capabilities (Perl, Tcl, Python) and proficiency in Linux/Unix environments;
Excellent analytical thinking, debugging, and problem solving skills;
Proven experience working effectively in large, cross functional teams while meeting aggressive project milestones.