Staff Engineer Functional Verification & Methodology

Staff Engineer Functional Verification & Methodology

Infineon

Munich, Germany

Your Role

Key responsibilities in your new role

• Create and define verification plans
• Develop the verification environment for our ICs using Universal Verification Methodology (UVM)
• Implement test scenarios using System Verilog and verify functionality using the constrained-random approach
• Develop assertions in System Verilog for formal verification
• Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies
• Enhance our pool of state-of-the-art verification methods
• Provide proactive support to internal stakeholders of our verification flow environment

Your Profile

Qualifications and skills to help you succeed

• A university degree in Electrical Engineering, Computer Science or similar
• At least 3 years of experience in Metric Driven Verification (digital and mixed signal)
• Capabilities and experience in working with microcontroller-based ICs, as well as with security and safety requirements
• Excellent know-how with UVM, especially using System Verilog
• Experience in technical leadership is a plus
• Knowledge in RTL design and firmware
• Excellent communication skills in English, German is a bonus