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Technical leadership of complex IP such as UCIe, Ethernet, HBM and PCIe; Collaborate with system architects and product managers to define the architecture and specifications on standards such as UCIe, considering factors such as data rate, power
Responsible for setting technical direction for end-to-end process integration across semiconductor manufacturing technologies. The role provides recognised technical leadership on process flow integration, module interactions, yield improvement, device
Senior, hands-on Network Engineer responsible for designing, deploying, and operating Cadence’s global enterprise network across data centres, campus environments, and WAN. This role focuses on delivering secure, highly available connectivity and