Principal Engineer, Design Verification Engineering

ADI - Analog Devices

Limerick or Valencia

About the role

In this position the successful candidate will be exposed to the entire product lifecycle from concept phase, through design, verification, implementation and release of products to customers. They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products. This is a senior role with the opportunity to create real impact within the organization and build a promising career. We're open to multiple locations.

Responsibilities

Verification of complex mixed signal designs and sub-systems using leading edge verification methodologies;
Architecting a unified verification testbench environment supporting both digital only and mixed signal verification requirements (UVM based);
Defining testplans, tests and verification methodology for chip-level verification. Working with the design team in generating test-plans and closure of code and functional coverage;
Continuous interaction with analog mixed signal and firmware teams;
Supporting post-silicon verification activities of the products working with design, product evaluation and applications engineering teams;
Tracking and management of design verification improvements;
Internal and External customer interaction/management;
Technically mentoring less-experienced verification engineers on SoC Verification responsible for block/IP-level DV.

Minimum Qualifications

Bachelor's or Master’s degree, in Engineering (Electronic Engineering) or equivalent;
10+ years ASIC design verification or related work experience.

Preferred Qualitifcations

Leadership skills enabling one to define, sell and implement a verification strategy;
Demonstrated ability to communicate with peers, managers, and project stakeholders effectively using both verbal and written communications;
Proficient in developing unit and SoC level test benches using UVM;
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology, formal verification;
Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, behavioral model validation and mixed-signal simulators like Cadence Xcelium;
Knowledge of SystemVerilog, digital simulation and debug;
Working with Cortex-M series based processors;
Gate Level Simulation (GLS) verification flow for SoC verification;
Pre and post-silicon verification testflow including HW, SW and FW;
Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting;
RTL design/front-end design/FPGA flow experience;
Experience in Matlab (including for co-simulation and HDL generation) and digital signal processing (e.g. development and verification for filters and Cordics);
Low power methodologies such as CPF/UPF;
Functional Safety requirements;
Excellent interpersonal and communication skills and the dream to take on diverse challenges;
Self-motivated and enthusiastic.