Senior Analog/Mixed-Signal PLL Design Engineer

Qualcomm

Cork, Ireland

The successful candidate will work on analog and mixed-signal integrated circuits for high-speed PLL IP for SoC and PHY level integration into Qualcomm's Mobile, Auto, IoT & Compute SoC products. The primary focus of the work is on low-power and low-voltage mixed-signal design with emphasis on advanced nanometer FinFET technology nodes.

The successful candidate will both design key circuit blocks and work closely with layout engineers to ensure the layout is fully optimized and complies with best analog layout practices. You will be directly involved in delivering next-generation PLL designs for Qualcomm SoCs and will be part of a large analog mixed-signal design team involved in architecture analysis and IP delivery in leading-edge FinFET process technology nodes at 3nm and beyond.

The role requires industry experience in transistor-level circuit implementations or highly relevant academic experience in a Masters’ or PhD program focused on full custom analog circuit design using nanometer CMOS technologies. In addition to Analog and Mixed-Signal circuit design expertise, good understanding of device physics, analog circuit custom layout, power distribution networks (PDN), mixed-signal design flow, SoC top-level integration and IC Design Tools are desired.

Responsibilities:

Architecture, design, and development of analog/mixed signal hard macros for the PLL IP Design team
Perform custom circuit design in the latest FinFET CMOS processes technologies and beyond to support the delivery of PLL IP
Participate in internal customer requirements discussions
Create design specifications
Create behavioural models in Verilog
Set-up, run and analyse circuit simulations
Perform quality assurance procedures on developed hard macros
Deliver hard macros and support customer integration and testing
Perform silicon characterization analysis and prepare silicon verification reports

Skills and Experience we would love to see:

Master’s or Ph.D. degree in Science, Engineering, or related field
A minimum of 3-years of transistor level analog mixed-signal design experience, preferably in PLL design, high-speed wireline SerDes, DDR or other high speed applications
Experience in SPICE simulators and schematic capture tools
Experience in designing op-amps, bandgaps, differential amplifiers, VCO, PLL, DLL
Understanding of signal integrity in high-speed wireline design is preferred
Scripting to automate circuit design and verification work
Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off
Excellent communication skills and ability to contribute strongly within a high-performance team

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