Senior Design Verification Engineer

Senior Design Verification Engineer

ADI - Analog Devices

Katowice, Poland

ADI’s drive to provide solutions for the next generation of 5G communications infrastructure, integration of ORAN in the network is a major step forward in adding value to the radio unit and related products. The added value from radio unit by ORAN IP cores is eCPRI and a LowPhy. Other algorithms will also play a role as the application evolves. These IP cores as well as others are used in ASIC’s within ADI as well as sold standalone to FPGA customers.

To support those activities within the Wireless Communication Business unit, we are seeking a Design Verification Engineer. The successful candidate will join an existing team with digital verification experts, algorithm, RTL, software, and systems architects. A central part of the role will be to extend the UVM environment, define, build, and execute test cases to cover the requirements set by the architects.

As a member of a very talented wireless system team, you will be at the heart of the chip design effort collaborating with all disciplines.  You will have the opportunity to engage with the wider aspects of the system and product development including design/test and documentation.  It's required that you communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. We also require additional responsibilities such as running regressions, tracking bugs, and analyzing coverage to achieve and bring the IP cores to a real-world quality implementation for our internal as well as external customers.

PRINCIPAL RESPONSIBILITIES 

  • Define block and chip level verification strategies based on design requirements and architecture
  • Maintain and enhance test bench environment(s)
  • Develop directed, random, and constrained random tests, and provide test reports
  • Implement Coverage driven verification methodologies. Come up with functional coverage metrics
  • Develop test plans, and all necessary tools and scripts to write, execute and debug tests including with on-chip embedded processors
  • Employ formal verification methods such as assertions
  • Run RTL and gate simulations based on use case scenarios, and debug failures
  • Work with designers to achieve code coverage targets
  • Work with senior DV engineer(s) to assess new tools and methods to improve existing verification methodologies

Qualifications 

Candidate Credentials 

  • BS/MS/PhD or Dipl.-Ing/Dr.-Ing in Electrical Engineering or equivalent education with 3 to 10 years of relevant experience including some or all the following aspects: 
  • Experience with communication systems and 4G or 5G is a plus
  • Experience with RTL designs and simulations
  • Knowledge of Verilog/System Verilog, digital simulation and debug.
  • Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
  • Excellent knowledge of Verilog, System Verilog and UVM
  • Experience with scripting languages such as Python and Tcl
  • Good knowledge of C / C++, matlab
  • Knowledge of standard ASIC verification flows including testbench development using UVM methodology, integrating C models using DPI, simulation, assertions, functional pattern generation for post silicon testing
  • Knowledge of testbench automation, bug tracking, and regression mechanisms
  • Excellent interpersonal skills and the dream to take on diverse challenges.
  • Ability to work independently to deliver the project goals.
  • Self-motivated team player with the ability to work independently and interface effectively with engineers across divisions and remote locations

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© EuroJobsites 2021

EuroJobsites is a registered company number: 4694396 VAT number: GB 880 9055 04

Registered address: EuroJobsites Ltd, Unit 8, Kingsmill Business Park, Kingston Upon Thames, London, KT1 3GZ, United Kingdom

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